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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
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Features * RoHS lead free and lead-solder-exempt products are available * Wide input voltage range: 3V-14V * High continuous output current: 7A * Wide programmable output voltage range: 0.5V-5.5V * Active digital current share * Output voltage margining * Overcurrent and overtemperature protections * Overvoltage and undervoltage protections, and Power Applications Good signal tracking the output voltage setpoint * Low voltage, high density systems with * Programmable power-up delay Intermediate Bus Architectures (IBA) * Tracking during turn-on and turn-off with guaranteed * Point-of-load regulators for high performance DSP, slew rates FPGA, ASIC, and microprocessor applications * Sequenced and cascaded modes of operation * Desktops, servers, and portable computing * Single-wire line for frequency synchronization * Broadband, networking, optical, and between multiple POLs communications systems * Programmable interleave * Active memory bus terminators ee * Programmable feedback loop compensation DataSh * Enable control with programmable polarity .com Benefits * Flexible fault management and propagation * Integrates digital power conversion with intelligent * Start-up into the load pre-biased up to 100% power management * Full rated current sink * Eliminates the need for external power management components and communication bus * Real time current and temperature measurements, monitoring, and reporting * Completely programmable via pin strapping and * Small footprint SMT package: 12.5x22mm external R and C * Low profile of 6.5mm * One part that covers all applications * Compatible with conventional pick-and-place * Reduces board space, system cost and equipment complexity, and time to market * Wide industrial operating temperature range * UL60950 recognized, CSA C22.2 No. 60950-00 certified, and TUV EN60950-1:2001 certified Description The ZY1207 is an intelligent, fully programmable step-down point-of-load DC-DC module integrating digital power conversion and intelligent power management. The ZY1207 completely eliminates the need for external components for sequencing, tracking, protection, monitoring, and reporting. Performance parameters of the ZY1207 are programmable by pin strapping and external resistor and capacitor and can be changed by a user at any time during product development and service without a need for a communication bus.
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
Reference Documents No-BusTM POL Converters. Z-1000 Series Application Note Z-OneTM POL Converters. Eutectic Solder Process Application Note Z-OneTM POL Converters. Lead-Free Process Application Note 1. Ordering Information
12 Series: No-Bus POL Converter 07 Output Current: 7A x Output voltage setpoint accuracy: No suffix - 1.5% or 35mV, whichever is greater. H1 - 1.5% or 20mV, whichever is greater y RoHS compliance: No suffix - RoHS compliant with Pb solder exemption2 G - RoHS compliant for all six substances - Dash zz 3 Packaging Option : T1 - 500pcs T&R T2 - 100pcs T&R T3 - 50pcs T&R Q1 - 1pc sample for evaluation only K1 - 1pc mounted on 4 the evaluation board
ZY Product family: Z-One Module
______________________________________ 1 2
Contact factory for availability. The solder exemption refers to all the restricted materials except lead in solder. These materials are Cadmium (Cd), Hexavalent chromium (Cr6+), Mercury (Hg), Polybrominated biphenyls (PBB), Polybrominated diphenylethers (PBDE), and Lead (Pb) used anywhere except in solder. 3 Packaging option is used only for ordering and not included in the part number printed on the POL converter label. 4 The evaluation board is available in only one configuration: ZY1207-K1.
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ee Example: ZY1207HG-T2: A 100-peices reel of RoHS compliant POL converters with the output voltage setpoint DataSh of 1.5% or 20mV, whichever is greater. Each POL converter is labeled ZY1207HG. .com
2.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect longterm reliability, and cause permanent damage to the POL converter.
Parameter Operating Temperature Input Voltage Output Current Conditions/Description Controller Case Temperature 250ms Transient (See Output Current Derating Curves) -7 Min -40 Max 105 15 7 Units C VDC ADC
3.
Environmental and Mechanical Specifications
Parameter Ambient Temperature Range Storage Temperature (Ts) Weight MTBF Peak Reflow Temperature Peak Reflow Temperature Lead Plating Moisture Sensitivity Level Calculated Per Telcordia Technologies SR-332 ZY1207 ZY1207G ZY1207 and ZY1207G JEDEC J-STD-020C 245 6.24 220 260 Conditions/Description Min -40 -55 Nom Max 85 125 8 Units C C grams MHrs C C
1.5m Ag over 1.5m Ni 2
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
4.
Electrical Specifications
Specifications apply at the input voltage from 3V to 14V, output load from 0 to 7A, ambient temperature from -40C to 85C, output capacitance consisting of 110F ceramic and 220F tantalum, and default performance parameters settings unless otherwise noted. 4.1 Input Specifications
Parameter Input voltage (VIN) Input Current (at no load) Undervoltage Lockout (VLDO connected to VIN) Undervoltage Lockout (VLDO connected to VAUX=5V) External Low Voltage Supply VLDO Input Current Conditions/Description At VIN<4.75V, VLDO pin needs to be connected to an external voltage source higher than 4.75V VIN4.75V, VLDO pin connected to VIN Ramping Up Ramping Down Ramping Up Ramping Down Connect to VLDO pin when VIN<4.75V Current drawn from the external low voltage supply at VLDO=5V 4.75 50 Min 3 50 4.00 3.9 2.8 2.7 14 Nom Max 14 Units VDC mADC VDC VDC VDC VDC VDC mADC
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4.2
Output Specifications
Parameter Output Current (IOUT) Output Voltage Range (VOUT) Output Voltage Setpoint Accuracy3 Line Regulation3 Load Regulation
3
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VIN MIN to VIN MAX Programmable2 with a resistor between TRIM and REF pins Default (no resistor) VIN=12V, IOUT=0.5*IOUT MAX, room temperature VIN MIN to VIN MAX 0 to IOUT MAX Slew rate 1A/s, 50-75% load step, VIN5V VIN=3.3V to 10% of peak deviation VIN=5.0V, VOUT2.5V VIN=5.0V, VOUT>2.5V VIN=12V, VOUT2.5V VIN=12V, VOUT>2.5V VIN=12V, IOUT=0.5*IOUT MAX
Min -7
1
Nom
Max 7 5.5
Units ADC VDC VDC
0.5 0.5
See Ordering Information 0.2 0.2 75 100 30 15 25 25 40 50 450 500 550 %VOUT %VOUT mV mV s mV mV mV mV ppm/C kHz
Dynamic Regulation Peak Deviation Peak Deviation Settling Time Output Voltage Peak-to-Peak Ripple and Noise BW=20MHz Full Load Temperature Coefficient Switching Frequency
1
At the negative output current (bus terminator mode) efficiency of the ZY1207 degrades resulting in increased internal power dissipation. Therefore maximum allowable negative current under specific conditions is 20% lower than the current determined from the derating curves shown in paragraph 5.5. 2 ZY1207 is a step-down converter, thus the output voltage is always lower than the input voltage as show in Figure 1. 3 Digital PWM has an inherent quantization uncertainty of 6.25mV that is not included in the specified static regulation parameters.
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
VOUT [V] 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Min Load 0.2A 0.5
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2.0
3.0
3.3
5.5
6.25
VIN [V] 8.0 10.0 12.0 14.0
4.0
6.0
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Figure 1. Output Voltage as a Function of Input Voltage and Output Current
4.3
Protection Specifications
Parameter Conditions/Description Output Overcurrent Protection Type Threshold Threshold Accuracy Output Overvoltage Protection Type Threshold Threshold Accuracy Delay Follows the output voltage setpoint Measured at VO.SET=2.5V From instant when threshold is exceeded until the turn-off command is generated Output Undervoltage Protection Type Threshold Threshold Accuracy Delay Follows the output voltage setpoint Measured at VO.SET=2.5V From instant when threshold is exceeded until the turn-off command is generated -2 6 Non-Latching, 130ms period 75 2 %VO.SET %VUVP.SET s -2 6 130
1
Min
Nom
Max
Units
Non-Latching, 130ms period 135 -25 25 %IOUT %IOCP.SET
Latching %VO.SET 2 %VOVP.SET s
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
Overtemperature Protection Type Turn Off Threshold Turn On Threshold Threshold Accuracy Delay From instant when threshold is exceeded until the turn-off command is generated Power Good Signal (PGOOD pin) Logic Lower Threshold Upper Threshold Delay Threshold Accuracy VOUT is inside the PG window and stable VOUT is outside of the PG window or ramping up/down Follows the output voltage setpoint Follows the output voltage setpoint From instant when threshold is exceeded until status of PG signal changes Measured at VO.SET=2.5V -2 High N/A Low 90 110 12 2 %VO.SET %VO.SET s %VO.SET Temperature is increasing Temperature is decreasing after module was shut down by OTP -5 6 Non-Latching, 130ms period 120 110 5 C C C s
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1
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Minimum OVP threshold is 1.0V
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4.4
Feature Specifications
Parameter
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Conditions/Description Current Share (CS pin) Min Nom Max Units
Type Maximum Number of Modules Connected in Parallel Current Share Accuracy IOUT MIN=0 IOUT MIN20%*IOUT NOM Interleave (IM and INTL2...INTL4 pins) Interleave (Phase Lag) Programmable via INTL2...INTL4 pins in 45 steps Sequencing (DELAY pin) Power-Up Delay Programmable by capacitor connected to DELAY pin Default: CDELAY=0 Tracking Rising Slew Rate Falling Slew Rate Proportional to SYNC frequency Proportional to SYNC frequency 0
Active, Single Line 4 20 %IOUT
315 210 0
degree ms ms
0.1 -0.5
V/ms V/ms
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
Enable (EN and ENP pins) ENP pin is pulled low EN Pin Polarity EN High Threshold EN Low Threshold Open Circuit Voltage Turn-On Delay Turn-Off Delay EN and ENP From EN pin changing state to VOUT starting to ramp up From EN pin changing state to VOUT reaching 0V Feedback Loop Compensation (CCA0...CCA2 pins) CCA=7 (default) CCA=6 Recommended VIN range Recommended COUT/ESR range, combination of ceramic+ tantalum Recommended VIN range Recommended COUT range, tantalum Recommended ESR range, tantalum Recommended VIN range Recommended COUT/ESR range, ceramic Recommended VIN range Recommended COUT/ESR range, .com combination of ceramic + tantalum Recommended VIN range Recommended COUT/ESR range, tantalum Recommended VIN range Recommended COUT/ESR range, ceramic Recommended VIN range Recommended COUT/ESR range, combination of ceramic+ tantalum 20%*IOUT NOM < IOUT < IOUT NOM VIN=12V Duty Cycle of the negative pulse corresponding to 100% of nominal current Temperature Monitoring (TEMP pin) Temperature Monitoring Accuracy Conversion Ratio Monitoring Voltage Range Output Impedance Junction temperature of POL controller Junction temperature from -40C to 140C Corresponds to -40C to 140C junction temperature range TEMP pin Remote Voltage Sense (+VS pin) Voltage Drop Compensation Between +VS and VOUT 300 mV 0.2 6.4 -5 10 2 +5 C mV/C VDC k 8 50/5 + 220/40 8 440 40 8 100/5 3 50/5 + 220/40 3 100/25 3 100/5 6 50/5 + 220/40 12 100/5 + 470/40 12 880 25 12 220/5 5 100/5 + 470/40 5 440/20 5 220/5 100/5 + 470/40 14 400/5 + 2000/20 14 10,000 10 14 400/5 5.5 200/5 + 880/40 5.5 1,000/10 5.5 400/5 11 200/5 + 880/40 VDC F/m F/m VDC F m VDC F/m VDC F/m F/m VDC F/m VDC F/m VDC F/m F/m 3.3 0 11 ENP pin is open Negative (enables the output when EN pin is pulled low) Positive (enables the output when EN pin is open or pulled high) 2.3 1.0 VDC VDC VDC ms ms
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CCA=5 CCA=3 or CCA=4 CCA=2 CCA=1 CCA=0
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Output Current Monitoring (CS pin) Output Current Monitoring Accuracy Conversion Ratio -20 70 +20 %IOUT %
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
4.5
Signal Specifications
Parameter VDD Conditions/Description Internal supply voltage SYNC Line ViL_s ViH_s Vhyst_s IoL_s Ipu_s Tr_s Cnode_s Freq_s Tsynq T0 LOW level input voltage HIGH level input voltage Hysteresis of input Schmitt trigger LOW level sink current V(SYNC)=0.5V Pull-up current source V(SYNC)=0V Maximum allowed rise time 10/90%VDD Added node capacitance Clock frequency of external SYNC line Sync pulse duration Data=0 pulse duration 475 22 72 5 -0.5 0.75 x VDD 0.25 x VDD 14 300 0.3 x VDD VDD + 0.5 0.45 x VDD 60 1000 300 10 525 28 78 V V V mA A ns pF kHz % of clock cycle % of clock cycle A V V V kOhm Min 3.15 Nom 3.3 Max 3.45 Units V
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Iup_x ViL_x ViH_x Vhyst_x RdnL_x
Inputs: INTL2...INTL4, CCA0...CCA2, EN, ENP, IM Pull-up current source V(X)=0 LOW level input voltage HIGH level input voltage Hysteresis of input Schmitt trigger External pull down resistance pin forced low Power Good and OK Inputs/Outputs Iup_PG Iup_OK ViL_x ViH_x Vhyst_x IoL_x Pull-up current source V(PG)=0 Pull-up current source V(OK)=0 LOW level input voltage HIGH level input voltage Hysteresis of input Schmitt trigger LOW level sink current at 0.5V Current Share/Sense Bus Iup_CS ViL_CS ViH_CS Vhyst_CS IoL_CS Tr_CS Pull-up current source at V(CS)=0V LOW level input voltage HIGH level input voltage Hysteresis of input Schmitt trigger LOW level sink current V(CS)=0.5V Maximum allowed rise time 10/90% VDD 0.84 -0.5 0.75 x VDD 0.25 x VDD 14 3.10 0.3 x VDD VDD+0.5 0.45 x VDD 60 100 mA V V V mA ns 25 175 -0.5 0.7 x VDD 0.1 x VDD 4 110 725 0.3 x VDD VDD+0.5 0.3 x VDD 20 A A V V V mA
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110 0.3 x VDD VDD+0.5 0.3 x VDD 10
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25 -0.5 0.7 x VDD 0.1 x VDD
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
5. 5.1
Typical Performance Characteristics Efficiency Curves
95 90 85
Efficiency, % 94 92 90 88 86 84 82 80
Efficiency, %
80 75 70 65 60 Vo=0.5V 55 0 1 2 3 4 5 6 7 Output Current, A Vo=1.2V Vo=2.5V
78 76 74 0 1 2 3 4 5 6 7 Output Current, A Vo=1.2V Vo=3.3V Vo=2.5V Vo=5.0V
Figure 4. Efficiency vs. Load. Vin=9.6V
92 90
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95 90 85 Efficiency, % 80 75 70 65 60 0
Figure 2. Efficiency vs. Load. Vin=3.3V
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Efficiency, %
88 86 84 82 80 78 76 74 72 Vo=1.2V Vo=3.3V 0 1 2 3 4 5 Vo=2.5V Vo=5.0V 6 7
Vo=0.5V Vo=2.5V 1 2 3
Vo=1.2V Vo=3.3V 4 5 6 7
70
Output Current, A
Output Current, A
Figure 5. Efficiency vs. Load. Vin=12V
Figure 3. Efficiency vs. Load. Vin=5V
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
95 90 85 Efficiency, % 80 75 70 65 60 55 0.5 1.5 2.5 3.5 4.5 5.5 Output Voltage, V
Figure 6. Efficiency vs. Output Voltage, Iout=7A
5.2
Turn-On Characteristics
Vin=5V Vin=9.6V
Vin=3.3V Vin=12V
Figure 8. Tracking Turn-On. Vin=12V, Ch1 - V1, Ch2 - V2, Ch3 - V3
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90 85 80 Efficiency, % 75 70 65 60 55 Vo=0.5V 50 3 4 5 6 7 8 9 10 11 12 13 14 Input Voltage, V
Figure 7. Efficiency vs. Input Voltage. Iout=7A
5.3
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Turn-Off Characteristics
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Vo=1.2V
Vo=2.5V
Figure 9. Tracking Turn-Off Vin=12V, Ch1 - V1, Ch2 - V2, Ch3 - V3
5.4
Transient Response
The pictures in Figure 10 - Figure 15 show the deviation of the output voltage in response to the 5075-50% step load at 1.0A/s. In all tests the POL converters had 5x22F ceramic capacitors and a 220F tantalum capacitor connected across the output pins. The speed of the transient response was optimized by selecting appropriate CCA settings.
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
Figure 10. Vin=12V, Vout=1V. CCA=00
Figure 13. Vin=5V, Vout=1V. CCA=03
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Figure 11. Vin=12V, Vout=2.5V. CCA=00
Figure 14. Vin=5V, Vout=2.5V. CCA=03
Figure 12. Vin=12V, Vout=5V, CCA=00
Figure 15. Vin=3.3V, Vout=1V. CCA=03
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
5.5
Thermal Derating Curves
7 6.5 Output Current, A 6 5.5 5 4.5 4 3.5
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3 45
0LFM
100LFM 55
200LFM 65
400LFM 75
600LFM 85
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Ambient Temperature, Degree C .com
Figure 16. Thermal Derating Curves. Vin=12V, Vout=5.0V
7 6.5 Output Current, A 6 5.5 5 4.5 4 3.5 3 45 0LFM 100LFM 55 200LFM 65 Ambient Temperature, Degree C
Figure 17. Thermal Derating Curves. Vin=14V, Vout=5.0V
400LFM 75
600LFM 85
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
6.
Typical Application
IBV ENABLE
CS TRIM VREF EN ENP CCA2 CCA1 CCA0 INTL4 INTL3 INTL2
SYNC
OK PGOOD TEMP VLDO VIN VIN VIN VIN VIN
CS TRIM VREF EN ENP CCA2 22uF 4.7uF 4.7uF CCA1 CCA0
SYNC
OK PGOOD TEMP VLDO VIN VIN VIN VIN VIN
POL2
+VS VOUT VOUT VOUT VOUT VOUT
POL4
+VS VOUT VOUT VOUT VOUT VOUT
22uF 4.7uF 4.7uF
INTL4 INTL3 INTL2 220uF 47uF 47uF IM DELAY
Vo2
220uF 47uF 47uF
IM DELAY
PGND PGND PGND PGND PGND PGND PGND
PGND PGND PGND PGND PGND PGND PGND
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CS TRIM VREF EN ENP CCA2 CCA1 CCA0 INTL4 INTL3 INTL2 SYNC OK PGOOD TEMP VLDO VIN VIN VIN VIN VIN
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CS TRIM VREF EN ENP CCA2
SYNC
OK PGOOD TEMP VLDO VIN VIN VIN VIN VIN
POL1
+VS VOUT VOUT VOUT VOUT VOUT
22uF 4.7uF 4.7uF
CCA1 CCA0 INTL4 INTL3
POL3
+VS VOUT VOUT VOUT VOUT VOUT
22uF 4.7uF 4.7uF
220uF IM DELAY PGND PGND PGND PGND PGND PGND PGND
47uF
47uF
Vo1
Vo3
220uF 47uF 47uF
INTL2
IM DELAY
PGND PGND PGND PGND PGND PGND PGND
Figure 18. Complete Schematic of Application with Three Independent Outputs. Intermediate Bus Voltage is from 8V to 14V.
In this application four POL converters are configured to deliver three independent output voltages. POL1 and POL2 are connected in parallel for increased output current. Output voltages are programmed with the resistors connected between TRIM and VREF pins of individual converters. POL1 is configured as a master (IM and INTL0...INTL4 pins are grounded) and all other POL converters are synchronized to the switching frequency of POL1. Interleave is programmed with pins INTL0...INTL4 to ensure the lowest input and output noise. POL2 has 180 phase shift, POL 3 and POL4 have phase shifts of 270 and 90 respectively. All converters are controlled by the common ENABLE signal. Turn-on and turn-off processes of the system are illustrated by pictures in Figure 8 and Figure 9.
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
7.
Pin Assignments and Description
Pin Name VLDO CCA0 CCA1 CCA2 TEMP ENP INTL2 INTL3 INTL4 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1923 24 2531 3236 Pin Type P I I I A I I I I I/O A I/O I/O I/O I A I A P I P P PU PU PU PU PU PU PU PU PU PU PU PU PU PU Buffer Type Pin Description Notes Connect to an external voltage source higher than 4.75V, if VIN<4.75V. Connect to VIN, if VIN4.75V Tie to PGND for 0 or leave open for 1 Tie to PGND for 0 or leave open for 1 Tie to PGND for 0 or leave open for 1 Analog voltage proportional to junction temperature of the controller Tie to PGND for Negative logic or leave open for Positive logic Tie to PGND for 0 or leave open for 1 Tie to PGND for 0 or leave open for 1 Tie to PGND for 0 or leave open for 1
Low Voltage Dropout Compensation Coefficient Address Bit 0 Compensation Coefficient Address Bit 1 Compensation Coefficient Address Bit 2 Temperature Measurement Enable Logic Selection Interleave Bit 2 Interleave Bit 3 Interleave Bit 4 Current Share/Sense Output Voltage Trim Power Good Frequency Synchronization Line Fault Status Enable Voltage Reference Interleave Mode Power-Up Delay Output Voltage Positive Voltage Sense Power Ground Input Voltage
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CS TRIM PGOOD SYNC OK EN VREF IM DELAY VOUT +VS PGND VIN
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Connect to CS pin of other Z-POLs connected ee in parallel DataSh To program the output voltage, connect a resistor between VREF and TRIM Connect to SYNC pin of other Z-POLs and/or to an external clock generator Connect to OK pin of other Z-1000 POLs. Leave open, if not used Polarity is determined by ENP pin To program the output voltage, connect a resistor between VREF and TRIM Tie to PGND for master or leave open to set interleave by INTL0...INTL4 pins Connect a capacitor between the pin and PGND to program the Power-Up delay. Leave open for zero delay
Connect to the positive point close to the load
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
8. 8.1
Pin and Feature Description VLDO, Low Voltage Dropout
fault occurs. Pulling low the OK input by an external circuitry turns off the POL converter. 8.10 SYNC, Frequency Synchronization Line The bidirectional input/output with the internal pull-up resistor. If the POL converter is configured as a master, the SYNC line propagates clock to other POL converters. If the POL converter is configured as a slave, the internal clock recovery circuit synchronizes the POL converter to the clock of the SYNC line. 8.11 PG, Power Good The open drain input/output with the internal pull-up resistor. The pin is pulled low by the POL converter, if the output voltage is outside of the window defined by the Power Good High and Low thresholds. 8.12 TRIM, Output Voltage Trim The input of the TRIM comparator for the output voltage programming.
The input of the internal linear regulator. VVLDO always needs to be greater than 4.75V for normal operation of the POL converter. 8.2 IM, Interleave Mode The input with the internal pull-up resistor. When the pin is left floating, the phase lag of the POL converter is set by INTL2...INTL4 pins. If the pin is pulled low, the phase lag is set to 0. Pulling all INTL pins and the IM pin low configures a POL converter as a master. The master determines the clock on the SYNC line. 8.3 TEMP, Temperature Measurement The voltage output of the internal temperature sensor measuring junction temperature of the controller IC. Voltage range from 0 to 2V corresponds to the temperature range from -50C to 150C.
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The output voltage can be programmed by a single resistor connected between VREF and TRIM pins. DataShee 8.4 ENP, Enable Polarity Resistance of the trim resistor can be determined The input with the internal pull-up resistor. When the .com the equation below: from ENP pin is pulled low, the control logic of the EN input is inverted. 20 x (5.5 - VOUT ) , kOhms RTRIM = 8.5 DELAY, Power-Up Delay VOUT The input of the POR circuit with the internal pull-up resistor. By connecting a capacitor between the pin where VOUT is the desired output voltage in Volts. and PGND the power-up delay can be programmed. If the RTRIM is open or the TRIM pin is shorted to 8.6 CCA[0:2], Compensation Coefficient PGND, the VOUT=0.5V. Address 8.13 CS, Current Share/Sense Bus Inputs with internal pull-ups to select one of 7 sets of digital filter coefficients application conditions. 8.7 optimized for various The open drain digital input/output with the internal pull-up resistor. The duty cycle of the digital signal is proportional to the output current of the POL converter. External capacitive loading of the pin shall be avoided. 8.14 INTL[2:4], Interleave Bits Inputs with internal pull-up resistors. The encoded number determines the phase lag of the POL converter when the IM pin is left floating. The phase lag is equal to the number multiplied by 45. 8.15 +VS The positive voltage input of the POL converter feedback loop.
VREF, Voltage Reference
The output of the 2V internal voltage reference that is used to program the output voltage of the POL converter. 8.8 EN, Enable The input with the internal pull-up resistor. The POL converter is turned off, when the pin is pulled low (see ENP to inverse logic of the Enable function). 8.9 OK, Fault Status The open drain input/output with the internal pull-up resistor. The POL converter pulls its OK pin low, if a
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
9. 9.1
Application Information Output Voltage Margining
RDOWN while the "Margining Up" switch is normally open disconnecting the resistor RUP. An alternative configuration of the margining circuit is shown in Figure 20. In this configuration both switches are normally open that may be advantageous in some implementations.
Margining can be implemented either by changing the trim voltage as described in the previous paragraph or by changing the resistance between the REF and TRIM pins.
Margining Down Switch (normally closed) Margining Up Switch (normally open) R UP R DOWN R TRIM TRIM
POL
REF
Margining Up Switch (normally open) R UP
REF R TRIM
POL
TRIM RDOWN Margining Down Switch (normally open)
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PGND
PGND
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Figure 19. Margining Configuration
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Figure 20. Alternative Margining Configuration
In the schematic shown in Figure 19, the nominal output voltage is set with the trim resistor RTRIM calculated from the equation in the paragraph 8.12. Resistors RUP and RDOWN are added to margin the output voltage up and down respectively and determined from the equations below.
RUP 20 x RTRIM 5 x RTRIM - V % = x , k 20 + RTRIM V %
RUP and RDOWN for this configuration are determined from the following equations:
RUP = 20 x RTRIM 5 x RTRIM - V % x , k V % 20 + RTRIM
R DOWN =
Caution:
20 x RTRIM 100 - V % x , k 20 + RTRIM V %
R DOWN
V % = (20 + RTRIM ) x , k 100 - V %
Noise injected into the TRIM node may affect accuracy of the output voltage and stability of the POL converter. Always minimize the PCB trace length from the TRIM pin to external components to avoid noise pickup.
where RTRIM is the value of the trim resistor in k and V% is the absolute value of desired margining expressed in percents of the nominal output voltage. During normal operation the resistors are removed from the circuit by the switches. The "Margining Down" switch is normally closed shorting the resistor
Refer to No-BusTM POL Converters. Z-1000 Series Application Note on www.power-one.com for more application information on this and other product features.
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REV. 1.3 MAR 27, 2006 www.power-one.com Page 15 of 18
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
10. Mechanical Drawings
All Dimensions are in mm Tolerances: 0.5-10 10-100 0.1 0.2
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ee DataSh
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Figure 21. Top (Left) and Bottom Views
6.50.30 2.1
8.7
12
Figure 22. Side View
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REV. 1.3 MAR 27, 2006 www.power-one.com Page 16 of 18
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
0.3
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1.00
22.80.10 (Bo)
40.40.10
440.20
5
ee DataSh
7.0
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1.1
Figure 23. Tape and Reel
22.20 2.00
36
19 0.60 (x 36) Top View 10.40
12.50
1
18
Pin 1 1.00 2.60
Figure 24. Recommended PCB Pad Sizes
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REV. 1.3 MAR 27, 2006 www.power-one.com Page 17 of 18
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ZY1207 7A No-Bus POL Data Sheet 3V to 14V Input * 0.5V to 5.5V Output
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Figure 25. Recommended PCB Layout for Multilayer PCBs
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Notes: 1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express written consent of the respective divisional president of Power-One, Inc. 2. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice.
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REV. 1.3 MAR 27, 2006 www.power-one.com Page 18 of 18

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